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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182 Group Under Development
Description The 32182 Group is a 32-bit, single-chip RISC microcomputer with built-in flash memory, which was developed for use in general industrial and household equipment. To accomplish high-precision arithmetic operations, it incorporates a fully IEEE754 compliant, single-precision FPU. This microcomputer contains a variety of peripheral functions ranging from 12-channel A-D converters, 37-channel multijunction timers, 10-channel DMACs, 4-channel serial I/Os, and 1-channel Real-time Debugger. Also included are 2-channel Full-CAN modules and JTAG (boundary scan facility). With the software necessary to run these numerous peripheral functions stored in its large-capacity flash memory, this microcomputer meets the needs of application systems for high functionality, high-performance arithmetic capability, and sophisticated control. With lower power consumption and low noise characteristics also considered, these microcomputers are ideal for embedded equipment applications. Features M32R-FPU core * Uses the M32R family RISC CPU core (M32R family common instruction set + single-precision FPU/extended instructions) * Five-stage pipelined processing * Sixteen 32-bit general-purpose registers * 16-bit/32-bit instructions implemented * DSP function instructions (multiply-Accumulate calculation using 56-bit accumulator) * Built-in single-precision FPU (fully compliant with IEEE754 standard: four rounding modes, etc.) * Bit manipulation extended instructions * Built-in flash memory * Built-in flash programming boot program * Built-in RAM * PLL clock generating circuit............................ Multiply by 8 * Oscillation stop detection function * Maximum operating frequency of the CPU clock M32182F8VFP/M32182F3VFP ............ 64MHz (when operating at -40C to +125C) M32182F8TFP/M32182F3TFP .............. 80MHz (when operating at -40C to +85C) * Single power supply: 5 V (+ 0.5 V) or 3.3 V (+ 0.3 V) Table 1. Type Name List (32182 Group) Type Name RAM Size M32182F8VFP/M32182F8TFP 64K bytes M32182F3VFP/M32182F3TFP 64K bytes SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 37-channel multijunction timers (MJT) Multijunction timers are incorporated that support various purposes of use. 16-bit output related timers (TOP) ................... 11 channels 16-bit input/output related timers (TIO)............ 10 channels 16-bit input related timers (TMS) ....................... 8 channels 32-bit input related timers (TML) ....................... 8 channels * Flexible configuration is possible through interconnection of timers. * The internal DMAC and A-D converter can be started by a timer. Real-time Debugger * Includes dedicated clock-synchronized serial I/O that can read and write the contents of the internal RAM independently of the CPU. * Can look up and update the data table in real time while the program is running. * Can generate a dedicated interrupt based on RTD communication. Abundant internal peripheral functions In addition to the timers and real-time debugger, the microcomputer contains the following peripheral functions. * DMAC ............................................................. 10 channels * A-D converters (Sample & hold function, Disconnection detector assist function, Injection current bypass circuit) ..................................... 12 channels 10-bit converter * Serial I/O ........................................................... 4 channels * Interrupt controller: 23 interrupt sources, 8 priority levels * Wait controller * Full CAN (CAN Specification 2.0B active)......... 2 channels * Virtual-Flash emulation function .......... 4K bytes x 8 banks * JTAG (boundary scan function, Mitsubishi original SDI debug function) * Port input threshold level select function Designed to operate at high temperatures To meet the need for use at high temperatures, the microcomputer is designed to be able to operate in the temperature range of -40 to +125C when CPU clock operating frequency = 64 MHz. When CPU clock operating frequency = 80 MHz, the microcomputer can be used in the temperature range of -40 to +85C. Note: * This does not guarantee continuous operation at 125C. If you are considering use of the microcomputer at 125C, please consult Mitsubishi. Applications Automobile equipment control (e.g., Engine, ABS, and AT), industrial equipment system control, and high-function OA equipment (e.g., PPC)
ROM Size 1024K bytes 384K bytes
2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182 Group Under Development
Pin Assignment (top view)
P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 VSS VCCE P44/CS0# P45/CS1# P224/A11/CS2# P225/A12/CS3# P46/A13 P47/A14 P30/A15 P31/A16 P32/A17 P33/A18 P34/A19 P35/A20 P36/A21 P37/A22 P20/A23 P21/A24 P22/A25 P23/A26 P24/A27 P25/A28 P26/A29 P27/A30 VCC-BUS VSS P93/TO16 P94/TO17 P95/TO18 P96/TO19 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
P174/TXD2 P175/RXD2 FP MOD0 MOD1 EXCVDD VSS EXCVCC VDDE VSS VCCE P17/DB15 P16/DB14 P15/DB13 P14/DB12 P13/DB11 P12/DB10 P11/DB9 P10/DB8 P07/DB7 P06/DB6 P05/DB5 P04/DB4 P03/DB3 P02/DB2 P01/DB1 P00/DB0 P73/HACK# P72/HREQ# P71/WAIT# P70/BCLK/WR# P43/RD# P42/BHW#/BHE# P41/BLW#/BLE# VCC-BUS VSS
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
M32182F8VFP M32182F8TFP M32182F3VFP M32182F3TFP
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
P97/TO20 P117/TO7 P116/TO6 P115/TO5 P114/TO4 P113/TO3 P112/TO2 P111/TO1 P110/TO0 P127/TCLK3 P126/TCLK2 P125/TCLK1 P124/TCLK0 EXCVCC VCCE VSS VSS SBI# P63 P62 P61 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AVSS0 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 VREF0 AVCC0
Note: * It is shown that the pin (signal) with which "#" sticks to the last of a pin name (signal name) is "L" active pin (signal).
Figure 1. Pin Layout Diagram
2
P150/TIN0 P153/TIN3 P130/TIN16 P131/TIN17 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21/RXD3 P136/TIN22/CRX1 P137/TIN23 P220/CTX0 P221/CRX0 VCCE VCNT OSC-VCC XIN OSC-VSS XOUT RESET# P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTDI JTDO JTRST JTCK JTMS P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1 P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Package 144P6Q-A
2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
M32R-FPU core (max. 80MHz)
Multiplier accumulator (32 x 16 + 56)
Internal bus interface
DMAC (10 channels)
Internal 32-bit bus
Single-precision FPU (fully IEEE754 compliant)
Input/output timer (37 channels)
Internal 32-bit bus
Internal flash memory
(M32182F8:1024K bytes) (M32182F3: 384K bytes)
A-D converter
(A-D0 : 10-bit,12 channels)
Internal 16-bit bus
Serial I/O (4 channels)
Internal RAM (64K bytes)
Interupt controller (8 priority levels)
Real-time debugger (RTD)
Wait controller
PLL clock generation circuit
Internal power supply generation circuit (VDC)
Full CAN (2 channels)
External bus interface
Data
Address
Input/output port 97 ports
Figure 2. Block diagram
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
Table 2. Outline Performance (1/2) Functional Block Features M32R-FPU core M32R family CPU core, internally configured in 32-bit Built-in multiplier-accumulator (32 x 16 + 56) Basic bus cycle: 15.625 ns (CPU clock frequency at 64 MHz, Internal peripheral clock frequency at 16MHz)
: 12.5 ns (CPU clock frequency at 80 MHz, Internal peripheral clock frequency at 20MHz)
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
External data bus Instruction set Internal flash memory Internal RAM DMAC
Multijunction timer
A-D converter
Serial I/O Real-time Debugger (RTD)
Interrupt controller Wait controller
CAN JTAG Clock
Logical address space: 4G bytes, linear General-purpose register: 32-bit register x 16,Control register: 32-bit register x 6 Accumulator: 56-bit 16-bit data bus 16-bit/32-bit instruction formats 100 discrete instructions in six addressing modes M32182F8VFP/M32182F8TFP: 1024K bytes M32182F3VFP/M32182F3TFP: 384K bytes Rewrite durability: 100 times 64K bytes 10 channels (DMA transfers between internal peripheral I/Os, between internal peripheral I/O and internal RAM, and between internal RAMs) Channels can be cascaded and can operate in combination with internal peripheral I/O 37 channels of multijunction timers. TOP : 16-bit output related timer, 11 channels (single-shot, delayed single-shot, and continuous) TIO : 16-bit input/output related timer, 10 channels (measure clear, measure free-run, noise processing input, PWM, single-shot, delayed single-shot, continuous output) TMS : 16-bit input related timer, 8 channels (measure input) TML : 32-bit input related timer, 8 channels (measure input) Flexible timer configuration is possible through interconnection of channels using the clock bus or event bus. 10-bit multifunction A-D converters * Input 12 channels * Scan-based conversion can be switched between N (N = 1-12) channels * Capable of interrupt conversion during scan * 8-bit/10-bit readout function * Sample & hold function * Disconnection detector assist function * Injection current bypass circuit 4 channels (The serial I/Os can be set for synchronous serial I/O or UART. SIO2, SIO3 are UART mode only) 1-channels dedicated clock-synchronized serial * Entire area of internal RAM Can access the internal RAM for read/rewrite from outside independently of the CPU, and also generate an exclusive-use interrupt. Controls interrupts from internal peripheral I/Os (Priority can be set to one of 8 levels including interrupt disabled) Controls wait when accessing external extended area (Chip selects for four external extended areas each can have access extended for 0-7 wait cycles plus WAIT# signal entered from external source) (Note 1) Two channels, each having 16-channel message slots Boundary-Scan function, Built-in SDI debugger function in MITSUBISHI M32182F8VFP, M32182F3VFP: CPU clock: maximum 64 MHz (for CPU, internal ROM, and internal RAM access) Internal peripheral clock (BCLK): maximum 16 MHz (for peripheral module access) External input clock (XIN): maximum 8.0 MHz, built-in x8 PLL circuit M32182F8TFP, M32182F3TFP: CPU clock: maximum 80 MHz (for CPU, internal ROM, and internal RAM access) Internal peripheral clock (BCLK): maximum 20 MHz (for peripheral module access) External input clock (XIN): maximum 10.0 MHz, built-in x8 PLL circuit
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
Table 2. Outline Performance (2/2) Functional Block Features Power Supply Voltage Operating temperature range (Note 2) 5V (+ 0.5V) or 3.3V (+ 0.3V) [T.B.D]: single power supply voltage (The internal logic operates with 2.5V, however) M32182F8VFP, M32182F3VFP: -40 to +125C (CPU clock 64MHz, internal peripheral clock 16MHz) M32182F8TFP, M32182F8TFP: -40 to +85C (CPU clock 80MHz, internal peripheral clock 20MHz) Package 0.5mm pitches / 144-pin LQFP package (144P6Q-A) Note 1: Wait Cycle by the external WAIT# input is not received when 0wait is selected. Moreover, as for all idol setup after the wait / strike robe / recovery / lead of CS block, only operation by "nothing" setup is guaranteed when 0wait is selected. Note 2: This does not mean that the microcomputer is guaranteed for continuous operation at 125C. If 125C applications are desired, please consult Mitsubishi. SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
XIN XOUT Clock VCNT OSC-VCC OSC-VSS Reset RESET# MOD0 Mode MOD1 P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1
5 8 4 5 5
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P93/TO16-P97/TO20 Port9 Multijunction timer Port10 Port8 Serial I/O
Data bus
Port0 Port1 Port2 Port3
P00/DB0-P07/DB7 P10/DB8-P17/DB15 P20/A23-P27/A30 P30/A15-P37/A22 P41/BLW#/BLE# P42/BHW#/BHE#
8
8 8 8
M32182F8VFP, M32182F8TFP, M32182F3VFP, M32182F3TFP
FP
P103/TO11-P107/TO15 P110/TO0-P117/TO7 P124/TCLK0-P127/TCLK3 P130/TIN16-P134/TIN20 P135/TIN21/RXD3 Port13 P136/TIN22/CRX1 P137/TIN23 Port11 Port12 CAN Serial I/O
Address bus
Bus Control
Port4
P43/RD# P44/CS0# P45/CS1# P46/A13, P47/A14
2
2
P150/TIN0, P153/TIN3 P174/TXD2 P175/RXD2 P220/CTX0 P221/CRX0 P224/A11/CS2# P225/A12/CS3#
Port15 Port17 Serial I/O
Port6 Interrupt Controller
P61-P63 SBI# P70/BCLK/WR#
3
CAN Port22 Address bus Bus Control
Bus Control Port7
P71/WAIT# P72/HREQ# P73/HACK# P74/RTDTXD
RTD
P75/RTDRXD P76/RTDACK P77/RTDCLK AD0IN0-AD0IN11
12
JTMS JTCK JTRST JTDO JTDI JTAG
A-D converter
AVCC0 AVSS0 VREF0 VDDE EXCVDD VCC-BUS
2 7 4 2
VSS VCCE EXCVCC
Note: * It is shown that the pin (signal) with which "#" sticks to the last of a pin name (signal name) is "L" active pin (signal).
Figure 3. Pin Function Diagram
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
Table 3. Description of Pin Function (1/3)
Type Power Supply Pin VCCE EXCVCC VCC-BUS VDDE EXCVDD VSS XIN XOUT BCLK Name Power supply External capacitance connect Bus power supply RAM power supply External capacitance connect Ground Clock input Clock output System clock Input/Output Input Output Output Function Power supply (5.0V 0.5V or 3.3V 0.3V). External capacitance connecting pin. Power supply for the bus control pins (5.0V 0.5V or 3.3V 0.3V). Internal RAM backup power supply (5.0V 0.5V or 3.3V 0.3V). Backup power supply for the internal RAM, external capacitance connecting pin. Connect all VSS pins to ground (GND). Clock input/output pins. These pins contain a PLL-based frequency multiply-by-8, so input the clock whose frequency is 1/8 the operating frequency. (XIN input = 10 MHz when CPU clock operates at 80 MHz) Outputs a clock twice the externally sourced clock frequency, XIN (when the internal CPU memory clock is 80 MHz, BCLK output = 20 MHz). Use this output when external sync design is desired. Power supply to the PLL circuit. Connect OSC-VCC to the power supply Connect OSC-VSS to ground. This pin controls the PLL circuit. Connect a resistor and capacitor to this pin. This pin resets the internal circuits. These pins set an operation mode. MOD0 MOD1 Mode 0 0 Single-chip mode 0 1 Expanded external mode 1 0 Processor mode (Boot mode) (Note 1) 1 1 (Do not select) Note: In boot mode, the FP pin must be at the high level. This pin protects the flash memory against E/W in hardware. To allow four blocks of up to 2 MB memory space each to be added externally, 20-bit address (A11-A30) is provided. A31 is not output. This is a 16-bit data bus connecting to an external device. During write cycle, the microcomputer outputs BHW# or BLW# to indicate the valid byte write position of the 16-bit data bus. During read cycle, the microcomputer always reads the full 16-bit data bus. Transferred to the internal circuit of the M32R, however, is the data at only the valid byte position. Chip select signals for external devices. This signal is output when reading external devices. This signal is output when writing external devices. Indicates the byte positions to which valid are transferred when writing to external devices. BHW#/ BHE# and BLW#/ BLE# correspond to the upper address side (DB0-DB7 effective) and the lower address side (DB8-DB15 effective), respectively. For external device access, it indicates that the upper byte data (DB0- DB7) is valid. For external device access, it indicates that the lower byte data (DB8- DB15) is valid. If WAIT# input is low when the M32R accesses external devices, the wait cycle extended. This pin is used by an external device to request control of the external bus. The M32R goes to a hold state when HREQ# input is pulled low. This signal indicates to the external device that the M32R has entered a hold state and relinquished control of the external bus.
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Clock
OSC-VCC OSC-VSS VCNT Reset Mode RESET# MOD0, MOD1
Clock power supply Clock ground PLL control Reset Mode
Input Input
Flash-only Address Bus Data bus
FP A11-A30 DB0-DB15
Flash Protect Address bus Data bus
Input Output Input/output
Bus Control
CS0#-CS3# RD# WR# BHW# BLW#
Chip select Read Write Byte High Write Byte Low Write
Output Output Output Output Output
BHE# BLE# WAIT# HREQ# HACK#
Byte High Enable Byte Low Enable Wait Hold request Hold acknowledge
Output Output Input Input Output
Note 1: In boot mode, the FP pin must be at the high level.
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
Table 3. Description of Pin Function (2/3)
Type Multijunction timer Pin TIN0, TIN3 TIN16-TIN23 TO0 -TO20 TCLK0 -TCLK3 A-D converter AVCC0 AVSS0 AD0IN0 -AD0IN11 VREF0 Interrupt controller Serial I/O SBI# SCLKI0/ SCLKO0 Timer clock Analog power supply Analog ground Analog input Reference voltage input System break interrupt UART transmit/receive clock output or CSIO transmit/receive clock input/output UART transmit/receive clock output or CSIO transmit/receive clock input/output Transmit data Receive data Transmit data Receive data Transmit data Receive data Transmit data Receive data Input Input Input Input Input/output Clock input pin for multijunction timers. AVCC0 is the power supply for the A-D0 converter. Connect AVCC0 to the power supply rail. AVSS0 is the analog ground for the A-D0 converters. Connect AVSS0 to ground. 16-channel analog input pins for the A-D0 converter in the first block. VREF0 is the reference voltage input pin for the A-D0 converter. System break interrupt (SBI) input pin of the interrupt controller When Channel 0 is in UART mode: Clock output derived from BRG output by dividing it by 2 When Channel 0 is in CSIO mode: Transmit/receive clock input when external clock is selected Transmit/receive clock output when internal clock is selected When Channel 1 is in UART mode: Clock output derived from BRG output by dividing it by 2 When Channel 1 is in CSIO mode: Transmit/receive clock input when external clock is selected Transmit/receive clock output when internal clock is selected Transmit data output pin of serial I/O channel 0 Receive data input pin of serial I/O channel 0 Transmit data output pin of serial I/O channel 1 Receive data input pin of serial I/O channel 1 Transmit data output pin of serial I/O channel 2 Receive data input pin of serial I/O channel 2 Transmit data output pin of serial I/O channel 3 Receive data input pin of serial I/O channel 3 Name Timer input Timer output Input/Output Input Output Function Input pin for multijunction timer Output pin for multijunction timer
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
SCLKI1/ SCLKO1
Input/output
TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 TXD3 RXD3
Output Input Output Input Output Input Output Input
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
Table 3. Description of Pin Function (3/3)
Type Real-time Debugger Pin RTDTXD RTDRXD RTDCLK RTDACK Name Transmit data Receive data Clock input Acknowledge Input/Output Output Input Input Output Function Serial data output pin of the Real-time Debugger Serial data input pin of the Real-time Debugger Serial data transmit/receive clock input pin of the Real-time Debugger This pin outputs a low pulse synchronously with the Real-time Debugger's first clock of serial data output word. The low pulse width indicates the type of the command/data the Real-time Debugger has received. Data output pin from CAN module. Data input pin to CAN module. Test select input for controlling the test circuit's state transition Clock input to the debugger module and test circuit. Test reset input for initializing the test circuit asynchronously. Serial output of test instruction code or test data. Serial input of test instruction code or test data. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. (However, P221 is an input-only port)
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
CAN
CTX0, CTX1 CRX0, CRX1
Transmit data Receive data Test mode Clock Test reset Serial output Serial input Input/output port 0 Input/output port 1 Input/output port 2 Input/output port 3 Input/output port 4 Input/output port 6 Input/output port 7 Input/output port 8 Input/output port 9 Input/output port 10 Input/output port 11 Input/output port 12 Input/output port 13 Input/output port 15 Input/output port 17 Input/output port 22
Output Input Input Input Input Output Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output
JTAG
JTMS JTCK JTRST JTDO JTDI
Input/output Port (Note 1)
P00-P07 P10-P17 P20-P27 P30-P37 P41-P47 P61-P63 P70-P77 P82-P87 P93-P97 P100-P107 P110-P117 P124-P127 P130-P137 P150, P153 P174, P175 P220, P221 P224, P225
Note 1: Input/output port 5 is reserved for future use. Input/output ports 14,16,18, 20 and 21 do not exist.
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
Outline of the CPU core The 32182 Group is built around the M32R RISC CPU core, and has the instruction set common to all of the M32R family microcomputers. To achieve high-precision arithmetic operation, this microcomputer additionally incorporates a fully IEEE754 compliant, single-precision FPU. Instructions are processed in five pipelined stages consisting of instruction fetch, decode, execution, memory access, and write back. Thanks to its "out-of-order-completion" mechanism, the M32R CPU allows clock cycle to realize efficient instruction execution control. The M32R-FPU internally contains sixteen 32-bit generalpurpose registers. The instruction set consists of 100 discrete instructions, which come in either 16-bit or 32-bit instruction format. Use of the 16-bit instruction format helps to reduce the program code size. Also, the availability of 32-bit instructions facilitates programming and increases the performance at the same clock speed, as compared to architectures with segmented address spaces. Multiply-Accumulate instructions comparable to DSP The M32R-FPU contains a multiplier/accumulator that can execute 32-bit x 16-bit in one cycle. Therefore, it executes a 32-bit x 32-bit integer multiplication instruction in three cycles. Also, the M32R-FPU supports the following four multiplyAccumulate instructions (or multiplication instructions) for DSP function use. (1) 16 high-order register bits x 16 high-order register bits (2) 16 low-order register bits x 16 low-order register bits (3) All 32 register bits x 16 high-order register bits (4) All 32 register bits x 16 low-order register bits Furthermore, the M32R-FPU has instructions for rounding the value stored in the accumulator to 16 or 32-bit, and instructions for shifting the accumulator value to adjust digits before storing in a register. Because these instructions also can be executed in one cycle, DSP comparable data processing capability can be obtained by using them in combination with high-speed data transfer instructions such as Load & Address Update or Store & Address Update. FPU instructions (12 instructions) The M32R-FPU supports single-precision, floating-point arithmetic operations fully compliant with IEEE754 standard. More specifically, it supports all of the following five exceptions and four rounding modes. Because the generalpurpose registers are used for floating-point arithmetic, data transfer overhead is reduced. * Five exceptions (invalid operation, division by zero, overflow, underflow, and inexact) * Four rounding modes (round toward nearest, round toward zero, round toward +, round toward -) 10 SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Also included are the floating-point multiply and add (FMADD) and floating-point multiply and subtract (FMSUB) instructions suitable for butterfly operation in FFT. Extended instructions (5 instructions) The M32R-FPU has several instructions implemented in it as extended instructions such as those to set, clear, and test bits, those to set and clear data in the processor status register, and those to automatically increment the address in which to store a halfword. Address space The 32182 Group's logical address is always handled in width of 32-bit, providing a linear address space of up to 4G bytes. The 32182's address space is divided into the following spaces. User space A 2G-byte area from H'0000 0000 to H'7FFF FFFF is the user space. Located in this space are the user ROM area, external extended area, internal RAM area, and SFR (Special Function Register) area (internal peripheral I/O registers). Of these, the user ROM area and external extended area are located differently depending on mode settings. System space A 2G-byte area from H'8000 0000 to H'FFFF FFFF is the system area. This space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and cannot be used by the user. Built-in flash memory and RAM The M32182F8VFP/M32182F8TFP contains 1024K bytes flash memory and 64K bytes RAM, the M32182F3VFP/ M32182F3TFP contains 384K bytes flash memory and 64K bytes RAM. The internal flash memory can be programmed while being mounted on the printed circuit board (on-board programming). Use of flash memory allows the same chip as those used in mass production to be used beginning with the development stage. This means that system development can be proceeded without having to change the printed circuit boards during the entire course, from prototype to mass production.
2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
Logical address H'0000 0000 Logical address H'0000 0000
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Single-chip mode
External extended Processor mode mode
16M bytes
H'000F FFFF H'0010 0000
Internal ROM (1024K bytes)
Internal ROM (1024K bytes)
CS0 area
CS0 area
2G bytes
User space
Ghost area in units of 16 bytes
H'001F FFFF H'0020 0000
CS1 area
CS1 area
H'7FFF FFFF H'8000 0000
H'003F FFFF H'0040 0000
CS2 area
CS2 area
2G bytes
System space
H'005F FFFF H'0060 0000
CS3 area
CS3 area
H'FFFF FFFF
H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000
SFR area (16K bytes) RAM area (64K bytes)
SFR area (16K bytes)
SFR area (16K bytes)
RAM area (64K bytes)
RAM area (64K bytes)
H'0081 3FFF H'0081 4000 H'0081 FFFF H'0082 0000
Reserved area (48k bytes)
Reserved area (48k bytes)
Reserved area (48k bytes)
Ghost area in units of 128k bytes
H'00FF FFFF
Figure 4. Address space of the M32182F8VFP/M32182F8TFP
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
Logical address H'0000 0000 Logical address
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Single-chip mode
External extended Processor mode mode
16M bytes
H'0000 0000 Internal ROM (384K) H'0005 FFFF H'0006 0000 Reserved area (640K bytes) H'000F FFFF H'0010 0000
Internal ROM (384K bytes) Reserved area (640K bytes)
CS0 area
CS0 area
2G bytes
User space
Ghost area in units of 16 bytes
H'001F FFFF H'0020 0000
CS1 area
CS1 area
H'7FFF FFFF H'8000 0000
H'003F FFFF H'0040 0000
CS2 area
CS2 area
2G bytes
System space
H'005F FFFF H'0060 0000
CS3 area
CS3 area
H'FFFF FFFF
H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000
SFR area (16K bytes) RAM area (64K bytes)
SFR area (16K bytes)
SFR area (16K bytes)
RAM area (64K bytes)
RAM area (64K bytes)
H'0081 3FFF H'0081 4000 H'0081 FFFF H'0082 0000
Reserved area (48k bytes)
Reserved area (48k bytes)
Reserved area (48k bytes)
Ghost area in units of 128k bytes
H'00FF FFFF
Figure 5. Address space of the M32182F3VFP/M32182F3TFP
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Mitsubishi Microcomputers
32182Group Under Development
CS0# Pin function (Note 1) Logical address H'0000 0000 CS1# A11 / CS2# A12 / CS3# CS0# CS1# A11 / CS2# A12 / CS3#
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
CS0# CS1# A11 / CS2# A12 / CS3#
CS0# CS1# A11 / CS2# A12 / CS3#
Internal ROM (1024K bytes)
Internal ROM (1024K bytes)
Internal ROM (1024K bytes)
Internal ROM (1024K bytes)
H'000F FFFF H'0010 0000 CS0 area (512K bytes) CS0 area (1M bytes) CS0 area (1M bytes) CS0 area (512K bytes)
H'001F FFFF H'0020 0000 CS1 area (512K bytes) CS1 area (1M bytes) CS1 area (512K bytes)
CS1 area (2M bytes) CS1 area (512K bytes)
H'003F FFFF H'0040 0000 CS2 area (512K bytes) CS2 area (1M bytes)
H'005F FFFF H'0060 0000 CS3 area (512K bytes) CS3 area (512K bytes)
CS3 area (512K bytes)
H'007F FFFF Note 1: The pin functions enclosed in are effective.
Figure 6. Internal ROM and External Extended Area when External Extended Mode (M32182F8VFP/M32182F8TFP) 13
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Mitsubishi Microcomputers
32182Group Under Development
CS0# Pin function (Note 1) Logical address H'0000 0000 H'0005 FFFF H'0006 0000 CS1# A11 / CS2# A12 / CS3# Internal ROM (384K bytes) CS0# CS1# A11 / CS2# A12 / CS3# Internal ROM (384K bytes)
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
CS0# CS1# A11 / CS2# A12 / CS3# Internal ROM (384K bytes)
CS0# CS1# A11 / CS2# A12 / CS3# Internal ROM (384K bytes)
Reserved area (640K bytes) H'000F FFFF H'0010 0000
Reserved area (640K bytes)
Reserved area (640K bytes)
Reserved area (640K bytes)
CS0 area (512K bytes) CS0 area (1M bytes) CS0 area (1M bytes)
CS0 area (512K bytes)
H'001F FFFF H'0020 0000 CS1 area (512K bytes) CS1 area (1M bytes) CS1 area (512K bytes)
CS1 area (2M bytes) CS1 area (512K bytes)
H'003F FFFF H'0040 0000 CS2 area (512K bytes) CS2 area (1M bytes)
H'005F FFFF H'0060 0000 CS3 area (512K bytes) CS3 area (512K bytes)
CS3 area (512K bytes)
H'007F FFFF Note 1: The pin functions enclosed in are effective.
Figure 7. Internal ROM and External Extended Area when External Extended Mode (M32182F3VFP/M32182F3TFP) 14
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Mitsubishi Microcomputers
32182Group Under Development
CS0#
Pin function (Note 1)
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
CS0# CS1# A11 / CS2# A12 / CS3#
CS0# CS1# A11 / CS2# A12 / CS3#
CS0# CS1# A11 / CS2# A12 / CS3#
CS1# A11 / CS2# A12 / CS3#
H'0000 0000 CS0 area (512K bytes) CS0 area (1M bytes) CS0 area (2M bytes) CS0 area (512K bytes) CS0 area (512K bytes)
H'001F FFFF H'0020 0000 CS1 area (512K bytes) CS1 area (1M bytes) CS1 area (2M bytes) CS1 area (512K bytes) CS1 area (512K bytes)
H'003F FFFF H'0040 0000 CS2 area (512K bytes) CS2 area (1M bytes)
H'005F FFFF H'0060 0000 CS3 area (512K bytes) CS3 area (512K bytes)
CS3 area (512K bytes)
H'007F FFFF
Note 1: The pin functions enclosed in are effective.
Figure 8. External Extended Area when Processor Mode 15
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Mitsubishi Microcomputers
32182Group Under Development
0 7 +0 address
8 15 +1 address
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
0
7 +0 address
8
15 +1 address
H'0080 0000 Interrupt controller (ICU) H'0080 007E H'0080 0080 A-D0 converter
H'0080 00EE
H'0080 0FE0 H'0080 0FFE H'0080 1000
MJT(TML1)
CAN0 H'0080 11FE H'0080 1400
H'0080 0100
Serial I/O
H'0080 0146
CAN1 H'0080 15FE
H'0080 0180 H'0080 0186 H'0080 01E0
H'0080 01F8 H'0080 0200
Wait Controller H'0080 3FFE Flash control
H'0080 023E H'0080 0240
MJT(common part)
MJT(TOP) H'0080 02FE H'0000 0300 MJT(TIO) H'0080 03BE H'0080 03C0 H'0080 03DE H'0080 03E0 H'0080 03FE H'0080 0400
Multi-junction timer (MJT)
MJT(TMS) MJT(TML0)
DMAC H'0080 0478 H'0080 0700 Input/output ports H'0080 0786
Note: * The Real-time debugger (RTD) is an independent module operated from external circuits, and is transparent to the CPU.
Figure 9. SFR Area
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32182Group Under Development
Built-in 37-channel multijunction timers (MJT) The microcomputer contains a total of 37 channels of multijunction timers consisting of 11 channels of 16-bit output related timers, 10 channels of 16-bit input/output related timers, 8 channels of 16-bit input related timers, 8 channels of 32-bit input related timers. Each timer has multiple operation modes to choose from, depending on the purposes of use. SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Also, the multijunction timers internally have a clock bus, input event bus, and an output event bus, so that multiple timers can be used in combination allowing for a flexible timer configuration. The output related timers have a correcting function that allows the timer's count value to be incremented or decremented as necessary while count is in progress, making real-time output control possible.
Table 4. Outline of the MJT Name Type TOP (Timer Output) Output related 16-bit timer (down-counter)
Number of channels 11
Contents One of three output modes is selected in software. * Single-shot output mode * Delayed single-shot output mode * Continuous output mode One of three input modes and four output modes is selected in software. * Measure clear input mode * Measure free-run input mode * Noise processing input mode * PWM output mode * Single-shot output mode * Delayed single-shot output mode * Continuous output mode 16-bit input measure timer.
TIO (Timer Input Output)
Input/output related 16-bit timer (downcounter)
10
TMS (Timer Measure Small) TML (Timer Measure Large)
Input related 16-bit timer (up-counter) 32-bit timer (up-counter)
8
8
32-bit input measure timer.
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32182Group Under Development
16-bit output related timer: 11 channels 16-bit input/output related timer: 10 channels 16-bit input related timer: 8 channels 32-bit input related timer: 8 channels
Input event bus
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Output event bus
Clock bus
To DMA and A-D converter
TCLK pin
E/L
Interrupt output CLK EN
Timer
F/F
T O pin
1/2 internal peripheral clock
PRS CLK
Timer
Interrupt output EN E/L F/F T O pin
: Edge/level selector : Prescaler : Junction box (selector)
TIN pin
E/L
PRS
F/F
: Output flip-flop
Note: * This is a conceptual diagram and does not show the actual timer configuration.
Figure 10. Conceptual Diagram of the Multijunction Timers (MJT)
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32182Group Under Development
Clock bus
3210
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Input event bus
3210
Output event bus
IRQ2
0123
clk
S
en en en en en en
en
TOP 0 TOP 1 TOP 2 TOP 3 TOP 4 TOP 5
TOP 6
udf
IRQ2
F/F0
F/F1
IRQ2
TO0 (P110)
TO1 (P111) TO2 (P112) TO3 (P113) TO4 (P114) TO5 (P115) TO6 (P116)
TCLK0 (P124)
TCLK0S
clk clk
udf udf
IRQ2
F/F2
F/F3
IRQ2
IRQ9
TIN0 (P150)
TIN0S
DMA3,DMA commonness
PRS0
S
clk clk clk
udf udf
IRQ2
F/F4
F/F5
IRQ1
BCLK/2
PRS1
PRS2
udf
udf
IRQ1
S
S
S
S
clk
S
F/F6
clk
en
TOP 7
udf
IRQ6
S
F/F7
TO7 (P117)
clk
clk
clk
en
en
en
TOP 8
TOP 9
TOP 10
TIO 0
TIO 1
TIO 2
TIO 3
TIO 4
udf
IRQ6
S
S
IRQ5
F/F8
F/F9
F/F10
F/F11
F/F12
F/F13
F/F14
TO8 (P100) TO9 (P101) TO10 (P102) TO11 (P103) TO12 (P104) TO13 (P105) TO14 (P106)
S
udf
udf
IRQ0
S
S
IRQ0
S
IRQ12
clk
S
TIN3 (P153)
TIN3S
DMA1
en/cap
en/cap
en/cap
en/cap
en/cap
udf
udf
IRQ0
clk
S
S
S
IRQ0
clk
S
udf
udf
IRQ4
clk
S
S
clk
S
udf
S
F/F15
TO15 (P107)
S
TCLK1 (P125)
TCLK1S
IRQ4
S
S
clk
en/cap
TIO 5
udf
IRQ4
S
F/F16
TO16 (P93)
TCLK2 (P126)
TCLK2S
S
S
clk
en/cap
TIO 6
udf
IRQ4
S
F/F17
TO17 (P94)
S
S
S
S
clk
en/cap
TIO 7
udf
DMA0 DMA commonness IRQ3
S
F/F18
TO18 (P95)
clk
en/cap
TIO 8
udf
IRQ3
S
F/F19
TO19 (P96)
S
S
3210 3210
clk
en/cap
TIO 9
udf
0123 : Selector
F/F20
TO20 (P97)
PRS0-2
: Prescaler
F/F
: Output flip-flop
S
Notes: * IRQn denote interrupt signals, with the same number representing interrupts in the same group. DMA0-9 and DMA common denote DMA requests to the DMAC. AD0TRG denote trigger signal for the A-D0 converter. * Denotes the edge select output of timer input pins. * Denotes input signals from the peripheral circuits (AD and SIO).
Figure 11. Block Diagram of MJT (1/3)
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Mitsubishi Microcomputers
32182Group Under Development
Clock abas
3210
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Input event bus
3210
Output event bus
0123
TCLK3
TCLK3S
S
S
clk
cap3
TMS 0 cap2 cap1
IRQ7
cap0
ovf
S
S
S
S
IRQ10
clk
cap3
S
cap2
TMS 1 cap1
IRQ7
cap0
ovf
TIN16
TIN16S
IRQ10
TIN17
TIN17S
IRQ10
S
TIN18
TIN18S
DMA2 IRQ10
S
TIN19
BCLK/2
TIN19S
DMA4
S
DMA5
S
clk cap3
IRQ11
TML0(32-bit) cap2 cap1
cap0
TIN20
TIN21
TIN22
TIN23
TIN20S TIN21S
S
IRQ11
S
IRQ11
TIN22S
IRQ11
S
S
AD0TRG
TIN23S
(To A-D0 converter)
BCLK/2
S
clk cap3
TML1(32bit) cap2 -cap1
cap0
S
S
S
S
AD0TRG
(To A-D0 converter)
AD0TRG(To A-D0 converter) AD0TRG(To A-D0 converter)
3210
3210
0123
Figure 12. Block Diagram of MJT (2/3)
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32182Group Under Development
Input event bus
3210
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Output event bus
0123
TIO8_udf TIN0S AD0 completed CAN0_S0/S15
S
AD0 completed TIO8_udf Started in software
S
DMA0
udf end
TIN3S
S
Started in software
S
DMA1
udf end
CAN0_S1/S14 TIN18S Started in software
S
S
DMA2
udf end
TIN0S
S
SIO0_TXD SIO1_RXD Started in software
S
DMA3
udf end
TIN19S SIO0_TXD
S
SIO0_RXD Started in software
S
DMA4
udf end
DMA0-4 interrupt
TIN20S Started in software
S
SIO2_RXD
S
DMA5
udf end
SIO1_RXD SIO1_TXD
S
Started in software
S
DMA6
udf end
SIO3_TXD SIO2_TXD
S
Started in software
S
DMA7
udf end
SIO3_RXD
S
Started in software
S
DMA8
udf end
SIO3_TXD
S
Started in software
S
DMA9
udf end
DMA5-9 interrupt
0123
3210
Figure 13. Block Diagram of MJT (3/3)
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Mitsubishi Microcomputers
32182Group Under Development
Built-in 10-Channel DMAC The microcomputer contains 10 channels of DMAC, allowing for data transfer between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs. DMA transfer requests can be issued from the user-created software, as well as can be triggered by a signal generated by the internal peripheral I/O (A-D converter, timer, or serial I/O). SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
The microcomputer also supports cascaded connection between DMA channels (starting DMA transfer on a channel at end of transfer on another channel). This makes advanced transfer processing possible without causing any additional CPU load.
Table 5. Outline of the DMAC Item Number of channels Transfer request
Content 10 channels * Software trigger * Request from internal peripheral I/O: A-D converter, timer, or serial I/O (reception completed, transmit buffer empty) * Cascaded connection between DMA channels possible (Note 1) Maximum number of times transferred 65536 times Transferable address space * 64K bytes (address space from H'0080 0000 to H'0080 FFFF) * Transfers between internal peripheral I/Os, between internal RAM and internal peripheral IO, and between internal RAMs are supported Transfer data size 16-bit or 8-bit Transfer method Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual-address transfer Transfer mode Single transfer mode Direction of transfer One of three modes can be selected for the source and destination of transfer: * Address fixed * Address increment * 32-channel ring buffer Channel priority Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 (Fixed priority) Maximum transfer rate 13.3M bytes per second (when internal peripheral clock = 20 MHz) Interrupt request Group interrupt request can be generated when each transfer count register underflows Note 1: The following DMA channels can be cascaded. DMA transfer on channel 1 started at end of one DMA transfer on channel 0 DMA transfer on channel 5 started at completion of all DMA transfers on channel 0 (transfer count register underflow) DMA transfer on channel 2 started at end of one DMA transfer on channel 1 DMA transfer on channel 0 started at end of one DMA transfer on channel 2 DMA transfer on channel 3 started at end of one DMA transfer on channel 2 DMA transfer on channel 4 started at end of one DMA transfer on channel 3 DMA transfer on channel 6 started at end of one DMA transfer on channel 5 DMA transfer on channel 7 started at end of one DMA transfer on channel 6 DMA transfer on channel 5 started at end of one DMA transfer on channel 7 DMA transfer on channel 8 started at end of one DMA transfer on channel 7 DMA transfer on channel 9 started at end of one DMA transfer on channel 8
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32182Group Under Development
Input event bus
3210
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Output event bus
0123
TIO8_udf TIN0S AD0 completed CAN0_S0/S15
S
AD0 completed TIO8_udf Started in software
S
DMA0
udf end
TIN3S
S
Started in software
S
DMA1
udf end
CAN0_S1/S14 TIN18S Started in software
S
S
DMA2
udf end
TIN0S
S
SIO0_TXD SIO1_RXD Started in software
S
DMA3
udf end
TIN19S SIO0_TXD
S
SIO0_RXD Started in software
S
DMA4
udf end
DMA0-4 interrupt
TIN20S Started in software
S
SIO2_RXD
S
DMA5
udf end
SIO1_RXD SIO1_TXD
S
Started in software
S
DMA6
udf end
SIO3_TXD SIO2_TXD
S
Started in software
S
DMA7
udf end
SIO3_RXD
S
Started in software
S
DMA8
udf end
SIO3_TXD
S
Started in software
S
DMA9
udf end
DMA5-9 interrupt
0123
3210
Figure 14. Block Diagram of DMAC 23
2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
12-channel A-D Converters The microcomputer contains 12-channel A-D converters with 10-bit resolution. In addition to single conversion on each channel, continuous A-D conversion on a combined group of N (N = 1-12) channels is possible. The A-D converted value can be read out in either 10-bit or 8-bit. In addition to ordinary A-D conversion, the converters support comparator mode in which the set value and A-D converted value are compared to determine which is larger or smaller than the other. SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Moreover, there is also Sample & hold function, input voltage is sampled, when A-D conversion is started, and the AD conversion of the sampling voltage is carried out. Since there is no invalid domain near [which becomes a problem by the external operational amplifier etc.] VCCE/VSS, conversion by the full range is possible in this sample & hold circuit. When A-D conversion is finished, the converters can generate a DMA transfer request, as well as an interrupt. The A-D converters are interfaced using a dedicated power supply to allow for connections to the peripheral circuits operating with 5 V.
Table 6. Outline of the A-D Converters Item Content Analog input 12-channel A-D conversion method Successive approximation method Resolution 10-bit (Conversion results can be read out in either 10 or 8-bit) Absolute accuracy (conditions: During low speed mode: Normal mode: + 2 LSB, double speed mode: + 2 LSB (Note 1) Ta = 25C, AVCC0, 1 = During high speed mode: Normal mode: + 3 LSB, double speed mode: + 3 LSB (Note 1) VREF0, 1 = 5.12 V) Conversion mode A-D conversion mode, comparator mode Operation mode Single mode, scan mode Scan mode Single-shot scan mode, continuous scan mode Special mode Single mode forcible execution under scan mode operation, scan mode start after the single mode execution, conversion re-start Sample & hold function Input voltage is sampled when A-D conversion is started, and it is A-D conversion about sampling voltage. Conversion start trigger Software start Started by setting A-D conversion start bit to 1 Hardware start MJT input event bus 2, MJT input event bus 3, MJT output event bus 3, and TIN23 Conversion Speed During single mode Low-speed Normal 299 x1/f(BCLK) (Note 2) f(BCLK) : Internal peripheral (Unavailable for Sample mode clock operating frequency & Hold Double speed 173 x1/f(BCLK) Available for Normal High-speed Normal 131 x1/f(BCLK) Sample & Hold) mode Double speed 89 x1/f(BCLK) During single mode Low-speed Normal 191 x1/f(BCLK) (Available for High-speed mode Sample & Hold) Double speed 101 x1/f(BCLK) High-speed Normal 95 x1/f(BCLK) mode Double speed 53 x1/f(BCLK) Normal 47 During comparator mode Low-speed x1/f(BCLK) mode Double speed 29 x1/f(BCLK) High-speed Normal 23 x1/f(BCLK) mode Double speed 17 x1/f(BCLK) Interrupt request generation When A-D conversion is finished, when comparate operation is finished When single-shot scan is finished, or when one cycle of continuous scan is finished DMA transfer request generaWhen A-D conversion is finished, when comparate operation is finished tion When single-shot scan is finished, or when one cycle of continuous scan is finished Note 1: The performance is the same during sample & hold function. Note 2: When XIN = 10 MHz, f(BLCK) = 20 MHz.
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32182Group Under Development
Internal date bus 8-bit readout Shifter AD0SIM0,1 AD0SCM0,1 AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0CMP 10-bit A-D0 Data Register 0 10-bit A-D0 Data Register 1 10-bit A-D0 Data Register 2 10-bit A-D0 Data Register 3 10-bit A-D0 Data Register 4 10-bit A-D0 Data Register 5 10-bit A-D0 Data Register 6 10-bit A-D0 Data Register 7 10-bit A-D0 Data Register 8 10-bit A-D0 Data Register 9 10-bit A-D0 Data Register 10 10-bit A-D0 Data Register 11 A-D Comparate Data Register A-D Control Circuit AVCC0 AVSS0
10-bit A-D Successive Approximation Register (AD0SAR) Mode selection Channel selectikon Conversion time selection
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
10-bit Readout
A-D0 Single Mode Register A-D0 Scan Mode Register AD0CTRG1
Input event bus3 Input event bus2 Output event bus3 TIN23
S
S
AD0STRG1
Interrupt request
VREF0
10-bit D-A Converter
Comparator
Flag control Interrupt control
DMA transfer request
AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11
DMA0 DMA commonness
Selector Sample & Hold control circuit
Successive Approximationtype A-D Converter Unit
Figure 15. Block Diagram of the A-D0 Converter
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Mitsubishi Microcomputers
32182Group Under Development
4-channel High-speed Serial I/Os The microcomputer contains 4 channels of serial I/Os consisting of four channels that can be set for CSIO mode (clock-synchronized serial I/O) or UART mode (asynchronous serial I/O) and two other channels that can only be set for UART mode. SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
The SIO has the function to generate a DMA transfer request when data reception is completed or the transmit register becomes empty, and is capable of high-speed serial communication without causing any additional CPU load.
Table 7. Outline of the Serial I/O Item Content Number of channels CSIO/UART: 2 channels (SIO0, SIO1) UART only : 2 channels (SIO2, SIO3) Clock During CSIO mode : Internal clock / external clock, selectable (Note 1) During UART mode: Internal clock only Transfer mode Transmit half-duplex, receive half-duplex, transmit/receive full-duplex BRG count source f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (When internal clock is selected) (Note 2) Data format CSIO mode: Data length = Fixed to 8-bit Order of transfer = Fixed to LSB first UART mode: Start bit = 1-bit Character length = 7, 8, or 9-bit Parity bit = With or without (If included, selectable between odd and even parity) Stop bit = 1 or 2-bit Order of transfer = Fixed to LSB first Baud rate CSIO mode: 152-bit per second to 2M-bit per second (when operating with f(BCLK) = 20 MHz) UART mode: 19-bit per second to 156K-bit per second (when operating with f(BCLK) = 20 MHz) Error detection CSIO mode: Overrun error only UART mode: Overrun, parity, and framing errors (The error-sum bit indicates which error has occurred) Fixed cycle clock output When SIO0 or SIO1 is in UART mode, this function outputs a 1/2 BRG clock from the SCLK pin. function Note 1: During CSIO mode, the maximum input frequency of an external clock is f(BCLK) divided by 16. Note 2: When f(BCLK) is selected for the BRG count source, the BRG set value is subject to limitations.
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32182Group Under Development
SIO0
SIO0 Transmit Buffer Register Transmit interrupt TXD0 SIO0 Transmit Shift Register Transmit /receive control circuit Receive interrupt To interrupt controller
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Transmit DMA transfer request Receive DMA transfer request
RXD0
SIO0 Receive Shift Register
To DMAC 3,DMAC4 To DMAC4
SIO0 Receive Buffer Register UART mode CSIO mode
When external clock selected When internal clock selected
BCLK
Clock divider
Baud rate generator (BRG)
CSIO mode When internal clock selected When UART mode selected
SIO1
TXD1 SIO1 Transmit Shift Register Transmit /receive control circuit Transmit interrupt Receive interrupt Transmit DMA transfer request Receive DMA transfer request
Internal data bus
BCLK, BCLK/8, BCLK/32, BCLK/256
1/16 1 (Set value + 1) 1/2 SCLKI0/ SCLKO0
To interrupt controller To DMAC6 To DMAC3,DMAC6 SCLKI1/ SCLKO1
RXD1
SIO1 Receive Shift Register
SIO2
TXD2 SIO2 Transmit Shift Register Transmit /receive control circuit Transmit interrupt Receive interrupt Transmit DMA transfer request Receive DMA transfer request To DMAC7 To DMAC5
RXD2
SIO2 Receive Shift Register
SIO3
Transmit interrupt TXD3 SIO3 Transmit Shift Register Transmit /receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request To DMAC9,DMA7 To DMAC8 To interrupt controller
RXD3
SIO3 Receive Shift Register
Note1: When BCLK is selected for the BRG count source,the BRG set value is subject to limitations. Note2: SIO2 and SIO3 do not have the SCLKI/SCLKO function.
Figure 16. Block Diagram of Serial I/O
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Mitsubishi Microcomputers
32182Group Under Development
Input/output Ports The microcomputer has a total of 97 input/output ports (of which P5 is reserved for future use). The input/output ports can be used as input ports or output ports by setting up their direction registers. Each input/output port is a dualSINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
function pin shared with other internal peripheral I/O or external extended bus signal lines. These pin functions are selected by using the chip operation mode select or the input/output port operation mode registers.
Table 8. Outline of Input/output Ports Item Specification Number of Total 97 ports Port P0 : P1 : P2 : P3 : P4 : P6 : P7 : P8 : P9 : P10 : P11 : P12 : P13 : P15 : P17 : P22 :
P00-P07 (8 lines) P10-P17 (8 lines) P20-P27 (8 lines) P30-P37 (8 lines) P41-P47 (7 lines) P61-P63 (3 lines) P70-P77 (8 lines) P82-P87 (6 lines) P93-P97 (5 lines) P100-P107 (8 lines) P110-P117 (8 lines) P124-P127 (4 lines) P130-P137 (8 lines) P150, P153 (2 lines) P174, P175 (6 lines) P220, P221, (4 lines) P224, P225 Port funcThe input/output ports can be set for input or output mode bit wise by using the input/output port direction contion trol register. (However, P221 is CAN0 input-only port.) Pin function Dual-functions shared with peripheral I/O or external extended signals (or multi-functions shared with peripheral I/Os which have multiple functions) Pin function P0-4, P224-P227: Changed by setting CPU operation mode (MOD0 and MOD1 pins) (Note 1) change P6-22 : Changed by setting the input/output port operation mode register (However, peripheral I/O over pin functions are selected using the peripheral I/O register.) Note 1: When the CPU is operating in external extended mode, P0-P4 and P224, and P225 by default are set for input/output port pins, but have their functions switched for external extended signal pins by setting the Port Operation Mode Register. When operating in single-chip or processor mode, the pin functions are switched over by setting the CPU operation mode pins as shown in Table 8.
Table 8. CPU Operation Modes and P0-P4, P224, P225 Pin Functions MOD0 MOD1 Operation mode P0-P4, P224, P225 pin function VSS VSS Single-chip mode Input/output port pin VSS VCCE External extended mode Input/output port pin or External extended signal pin VCCE VSS Processor mode (FP pin = VSS) External extended signal pin VCCE VCCE Do not select Note: * VCCE and VSS are connected to power supply and GND, respectively.
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Mitsubishi Microcomputers
32182Group Under Development
0 P0 P1
Settings of Chip operation mode (Note 1)
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
1 DB1 DB9 A24 A16 BLE# /BLW#
2 DB2 DB10 A25 A17 BHE# /BHW#
3 DB3 DB11 A26 A18 RD#
4 DB4 DB12 A27 A19 CS0#
5 DB5 DB13 A28 A20 CS1#
6 DB6 DB14 A29 A21 A13
7 DB7 DB15 A30 A22 A14
DB0 DB8 A23 A15
P2 P3 P4
Reserved
P5 P6 P7 P8 P9 P10 P11 P12 P13 TIN16 TIN17 TIN18 TIN19 TO8 TO0 TO9 /TXD3 TO1 TO10 /CTX1 TO2 WR# /BCLK MOD0 (Note 2) (P61) WAIT# MOD1 (Note 2) (P62) HREQ# TXD0 (P63) HACK# RXD0 TO16 TO11 TO3 SBI# (Note 2) RTDTXD RTDRXD RTDACK RTDCLK SCLKI0 /SCLKO0 TO17 TO12 TO4 TCLK0 TIN20 TXD1 TO18 TO13 TO5 TCLK1 TIN21 /RXD3 RXD1 TO19 TO14 TO6 TCLK2 TIN22 /CRX1 SCLKI1 /SCLKO1 TO20 TO15 TO7 TCLK3 TIN23
Settings of input/output port Operation Mode Register
P14 P15 P16 P17 P18 P19 P20 P21 P22 CTX0 CRX0 CS2#/A11 CS3#/A12
(Note 1) (Note 1)
TIN0
TIN3
TXD2
RXD2
Note: * P5, P14, P16, P18, P19, P20, and P21 do not exist. Note 1: Pin functions are switched over by setting MOD0 and MOD1 pins. Note 2: It cannot be used as a function of an input/output ports. The input level of SBI#, MOD0, and an MOD1 pin can be read.
Figure17. Input/Output Ports and pin function Assignments
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
CAN Modules The 32182 contains two blocks of Full-CAN modules compliant with CAN Specification V2.0B active. SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
The CAN modules each have 16 slots of Message Slot.
Data Bus
CAN0 Status Register
CAN0 REC Register
CAN0 TEC Register
CAN0 Message Slot 0-15 Control Register
CAN0 Extended ID Register
CAN0 Configuration Register
CAN0 Control Register
CAN0 Global Mask Register CAN0 Local Mask RegisterA
CAN0 Local Mask RegisterB
Message Memory
(1)Message ID (2)Date Code (3)Message Data (4)Time Stamp
CAN0 Slot Status Register
CAN0 slot Interrupt Control Register
CAN0 error Interrupt Control Register
Interrupt Control circuit
CTX0
CAN0 Protocol controller Ver 2.0B active
Acceptance filtering
16-bit Timer CAN0 Time Stamp Register
CRX0
CAN0 Transmit/Receive &Error Interrupt
Figure 18. Block Diagram of the CAN0 Module
Data Bus
CAN1 Status Register
CAN1 REC Register
CAN1 TEC Register
CAN1 Message Slot 0-15 Control Register
CAN1 Extended ID Register
CAN1 Configuration Register
CAN1 Control Register
CAN1 Global Mask Register CAN1 Local Mask RegisterA
CAN1 Local Mask RegisterB
Message Memory
(1)Message ID (2)Date Code (3)Message Data (4)Time Stamp
CAN1 Slot Status Register
CAN1 slot Interrupt Control Register
CAN1 error Interrupt Control Register
Interrupt Control circuit
CTX1
CAN1 Protocol controller Ver 2.0B active
Acceptance filltering
16-bit Timer CAN1 Time Stamp Register
CRX1
CAN1 Transmit/Receive &Error Interrupt
Figure 19. Block Diagram of the CAN1 Module
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Mitsubishi Microcomputers
32182Group Under Development
8-level Interrupt Controller The Interrupt Controller controls interrupt requests from each internal peripheral I/O (23 sources) by using eight priority levels assigned to each interrupt source, including interrupts prohibition. In addition to these interrupts, it handles System Break Interrupt (SBI), Reserved Instruction Exception (RIE), and Address Exception (AE) as nonmaskable interrupts. Wait Controller The Wait Controller supports access to external devices. For access to an external extended area of up to 8M bytes (during external extended or processor mode), the Wait Controller controls bus cycle extension by inserting zero to seven wait cycles and using external WAIT# signal input. However, as setup for lead of CS signal / lead of strobe signal / recovery / idol after lead cycle, only operation by "nothing" setup is guaranteed when 0wait is selected. Moreover, WAIT by the external WAIT input is not received when 0wait is selected. SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in clock frequency multiplier The PLL (clock frequency multiplier) multiplies the input clock frequency by 8 to generate the CPU memory clock. For the maximum CPU memory clock frequency of 80 MHz, the input clock frequency is 10.0 MHz. Three operation modes The 32182 Group has three operation modes: single-chip mode, external extended mode, and processor mode. These operation modes are changed from one to another by setting the MOD0 and MOD1 pins. Port input threshold level select function The port input level switch function sets the port threshold value to 3 different voltage levels (Schmidt ON/OFF selection also available).
0.7VCCE 0.5VCCE Pin
Input function enable
S S
VT+
Schmitt
VTS
PORT Input
0.35VCCE Threshold
S
VTnSELL
Standard input threshold level of peripheral function
PTnSEL
S WFnSEL
Peripheral function input
Figure 20. Port input threshold level select function
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Mitsubishi Microcomputers
32182Group Under Development
Real-time Debugger (RTD) The Real-time Debugger (RTD) provides a function for accessing directly from the outside to the internal RAM. It uses a dedicated clock-synchronized serial I/O to communicate with the outside. Use of the RTD communicating via dedicated serial lines allows the internal RAM to be read out and rewritten without having to halt the CPU. Also, it can activate an exclusive RTD interrupt through RTD communication. SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in Virtual-Flash emulation function The 384K bytes of internal flash memory can have its 4K bytes areas (total 96 banks) replaced with 4K bytes areas of the internal RAM (4K bytes x 8). Use of this function helps to make the necessary changes and evaluate the changed program during development phase without having to reset the microcomputer. Also, when combined with the Real-time Debugger, this function enables the data in RAM to be rewritten and read out without causing CPU load, making it possible to reduce the program evaluation period.
32182
RTDCLK RTDRXD
Command address
M32R CPU
Internal RAM
Virtual-DPRAM structure
Real-Time Debugger
Data
Data
(RTD)
RTDTXD RTDACK
Data
R/W without CPU intervention
Data Bus(CPU)
Data Bus(RTD)
Figure 21. Conceptual Diagram of the Real-time Debugger (RTD)

H'0080 4000
H'0000 0000 H'0000 1000 H'0000 2000
S bank 0 (4K bytes) S bank 1 (4K bytes) S bank 2 (4K bytes)
H'0080 7FFF
4K bytes 4K bytes 4K bytes
H'0080 8000 H'0080 9000 H'0080 A000 H'0080 B000 H'0080 C000 H'0080 D000 H'0080 E000 H'0080 F000
H'000F D000 H'000F E000 H'000F F000
S bank 253 (4K bytes) S bank 254 (4K bytes) S bank 255 (4K bytes)
4K bytes 4K bytes 4K bytes 4K bytes 4K bytes
Note: * The bank for M32182F3VFP/M32182F3TFP extends to s-bank95.
Figure 22. Conceptual Diagram of the Virtual -Flash Emulation (Units 4K bytes)
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Mitsubishi Microcomputers
32182Group Under Development
CPU Instruction Set The M32R employs a RISC architecture, supporting a total of 100 discrete instructions. (1) Load/store instructions Perform data transfer between memory and registers.
LD LDB LDUB LDH LDUH LOCK ST STB STH UNLOCK Load Load Load Load Load Load Store Store Store Store byte unsigned byte halfword unsigned halfword locked byte halfword unlocked ADD ADD3 ADDI ADDV ADDV3 ADDX NEG SUB SUBV SUBX
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER *Arithmetic operation
Add Add 3-operand Add immediate Add(with overflow checking) Add 3-operand Add with carry Negate Subtract Subtract (with overflow checking) Subtract with borrow
*Multiplication/division
DIV DIVU MUL REM REMU Divide Divide unsigned Multiply Remainder Remainder unsigned
(2) Transfer instructions Perform register to register transfer or register to immediate transfer.
LD24 LDI MV MVFC MVTC SETH Load 24-bit immediate Load immediate Move register Move from control register Move to control register Set high-order 16-bit
*Shift
SLL SLL3 SLLI SRA SRA3 SRAI SRL SRL3 SRLI Shift Shift Shift Shift Shift Shift Shift Shift Shift left logical left logical 3-operand left logical immediate right arithmetic right arithmetic 3-operand right arithmetic immediate right logical right logical 3-operand right logical immediate
(3) Branch instructions Used to change the program flow.
BC BEQ BEQZ BGEZ BGTZ BL BLEZ BLTZ BNC BNE BNEZ BRA JL JMP NOP Branch on C-bit Branch on equal Branch on equal zero Branch on greater than or equal zero Branch on greater than zero Branch and link Branch on less than or equal zero Branch on less than zero Branch on not C-bit Branch on not equal Branch on not equal zero Branch Jump and link Jump No operation
(5) Instructions for the DSP function Perform 32-bit x16-bit or 16-bit x 16-bit multiplication or multiply-Accumulate calculation. These instructions also perform rounding of the accumulator data or transfer between accumulator and general-purpose register.
MACHI MACLO MACWHI MACWLO MULHI MULLO MULWHI MULWLO MVFACHI MVFACLO MVFACMI MVTACHI MVTACLO RAC RACH Multiply-accumulate high-order halfwords Multiply-accumulate low-order halfwords Multiply-accumulate word and high-order halfword Multiply-accumulate word and low-order halfword Multiply high-order halfwords Multiply low-order halfwords Multiply word and high-order halfword Multiply word and low-order halfword Move from accumulator high-order word Move from accumulator low-order word Move from accumulator middle-order word Move to accumulator high-order word Move to accumulator low-order word Round accumulator Round accumulator halfword
(4) Arithmetic/logic instructions Perform comparison, arithmetic/logic operation, multiplication/division, or shift between registers. * Comparison
CMP CMPI CMPU CMPUI Compare Compare immediate Compare unsigned Compare unsigned immediate
(6) EIT related instructions Start trap or return from EIT processing.
RTE TRAP Return from EIT Trap
* Logical operation
AND AND3 NOT OR OR3 XOR XOR3 AND AND 3-operand Logical NOT OR OR 3-operand Exclusive OR Exclusive OR 3-operand
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Mitsubishi Microcomputers
32182Group Under Development
(7) Instructions for the FPU function The microcomputer supports fully IEEE-754 compliant, single-precision floating-point arithmetic.
FADD FSUB FMUL FDIV FMADD FMSUB ITOF UTOF FTOI FTOS FCMP FCMPE Floating-point add Floating-point subtract Floating-point multiply Floating-point divide Floating-point multiply and add Floating-point multiply and subtract Integer to float Unsigned to float Float to integer Float to short Floating-point compare Floating-point compare with exception if unordered STH BSET BCLR BTST SETPSW CLRPSW
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER (8) Extended instructions
Store halfword(@R+ addressing added) Bit set Bit clear Bit test Set PSW Clear PSW
Rsrc1 15 16 H L Rsrc2 15 16 H L

31 0 31 0 H x x
0
ACC
63
0
Rsrc1 15 16 L
31 0 H x
Rsrc2 15 16 L
31
MULHI instruction 0
ACC
MULLO instruction 63
x + +
Rsrc1 0 32bit 31 0 H
Rsrc2 15 16 L
0 31
MACHI instruction
ACC
MACLO instruction 63
0 x x MULHI instruction 0
ACC ACC
63
MULLO instruction 63
Rsrc1 0 32bit x x 31 0 H
Rsrc2 15 16 L
31
+ +

0
ACC
63
MACWHI instruction 0 ACC
MACWLO instruction 63
0
sign
RAC instruction data
63 0
0

MVFACMI instruction
0
ACC
63
15 16
31 32 ACC
47 48
63
0 Rsrc
31
0
sign
RACH instruction data
MVFACHI instruction
MVFACLO instruction 31 Rdest 0
MVTACHI instruction 31 32 ACC
MVTACLO instruction 63
63 0
0
Figure 23. Instructions for the DSP Function 34
2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group Under Development
Package Dimensions Diagram
144P6Q-A
MMP
JEDEC Code -
HD
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Plastic 144pin 20 x 20mm body LQFP
e
Weight(g) 1.23 Lead Material Cu Alloy
MD
EIAJ Package Code LQFP144-P-2020-0.50
108
73
109
72
b2
D
l2 Recommended Mount Pad
Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
144
37
1
36
A
F
L1
e
x y
y
b
x
M
L
Detail F
Lp
b2 I2 MD ME
Dimension in Millimeters Min Nom Max - - 1.7 0.125 0.2 0.05 1.4 - - 0.17 0.22 0.27 0.105 0.125 0.175 19.9 20.0 20.1 19.9 20.0 20.1 0.5 - - 21.8 22.0 22.2 21.8 22.0 22.2 0.35 0.5 0.65 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 0.1 - - 0 8 - 0.225 - - 0.95 - - 20.4 - - - - 20.4
HE
E
A2
A1
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. * Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. * All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). * When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. * Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. * The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. * If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. * Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
(c)2002 MITSUBISHI ELECTRIC CORP. New publication, effective Oct. 2002. Specifications subject to change without notice.
c
A3
ME
REVISION HISTORY
Rev. 1.0 1.2 Date Page 07/12/02 10/11/02 Entire page First Edition.
32182 Group Data Sheet
Description Summary
Add 1024KB version of Flash Memory product to line-up.
(1/1)

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